In semiconductor devices such as transistors, an isolation region is needed to prevent leakage current from occurring between devices. Shallow trench isolation (STI) structures have been widely used to form these isolation regions in semiconductor devices.
The STI structures are generally formed as follows. A pad dielectric pattern is formed on a silicon substrate. Shallow trenches are formed by etching the silicon substrate using the pad dielectric pattern as a mask. A dielectric layer is deposited to fill the trench. A planarization process is performed on the dielectric layer.
However, during such a procedure, the pad dielectric pattern may be easily damaged during the etching process of the silicon substrate. This damage causes a leakage problem in the devices.